Yokota-Ootsu Lab., Dept. of Information Systems Science, Grad. School of Engineering, Utsunomiya Univ.

PearLab, Utsunomiya Univ.

Japanese/ English

Platform for Embedded FPGA Design

Background

An efficient parallel processing using FPGA (Field Programmable Gate Array) is applied for many scenes such as high performance computations, real-time system designs and so on.  In order to handle FPGA, however, designing by HDL (Hardware Description Language) is normally required. Therefore software developers feel that threshold of FPGA is too high.

Outline

Our project researches methods to abstract FPGA programming hardware. By abstracting hardware on FPGA, software developers can use integrated circuits and computation resources as abstract parts. Moreover examples, which demonstrate operations of FPGA from host system, show efficiency of our proposed method for system development including FPGA. Based on design examples of distributed system, which operates FPGA from Java program on Android terminal, evaluation can be done from the view point of software engineering and design engineering. 

Projects

News

Project Leader

 Ohkawa, Takeshi (assistant professor)

Project Member 

 Yamashina, Kazushi (MC2)

 Matsumoto, Takuya (MC1)

 Kobayashi, Toki (B4)

 Sugata, Yuhei (B4)

-> ex members